Does the Floorplan of a Chip Affect Its Yield?
نویسندگان
چکیده
The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for seueml recently designed VLSI chips that incorpomte some defect tolemnce. The purpose of this paper is to investigate the relationship betweenfloorplanning and yield for this type of chips.
منابع مشابه
On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI...
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